(1) Technical Field
This disclosure relates to electronic circuits, and more particularly to integrated circuit designs and methods of design.
(2) Background
The translation of integrated circuit designs from circuit diagrams or hardware programming code to working integrated circuits (IC's) implemented in modern transistor technologies remains as much art as engineering. A significant challenge in fabricating IC's is to control circuit parameters (such as delay, transistor threshold voltage, and transistor transconductance parameters) in view of variations in the semiconductor fabrication process, IC supply voltage, and IC operating temperature (often abbreviated as “PVT”, for “Process”, “Voltage”, and “Temperature” parameters).
Process variations during IC manufacture can cause unpredictable and undesired variations of circuit parameters, which can adversely affect circuit performance. Process variation is the naturally occurring variation of the attributes of transistors (e.g., length and width dimensions, film and oxide thickness, doping concentrations, etc.) when integrated circuits are fabricated. In addition, the parameters of individual transistors vary from wafer-to-wafer (interprocess variation) and die-to-die (intraprocess variation). Process variation becomes particularly important at smaller process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the devices and as feature sizes approach fundamental dimensions, such as the size of atoms and the wavelength of usable light for patterning lithography masks.
All of the above parameters and variables generally exhibit complex relationships among each other. For example, attaining homogeneous transistor operating parameters, such as threshold voltage and transconductance, within an integrated circuit is one of the most important, yet most difficult, objectives for precision analog circuits. As another example, transistor threshold voltage is very critical in determining propagation speed for high speed, low voltage digital circuits.
In other words, circuit parameters tend to be process dependent. Thus, it is useful for a manufacturer to be able to quantify or determine process variations applicable to a particular IC design, taking into account a range of supply voltages and operating temperatures, in order to meet a design specification and maximize IC die yields for that design.
An important aspect of determining PVT parameters for an IC design is to determine “process corners” before commencing large scale production. A process corner refers to measured and categorized variations of various parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto a wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but the current design standard is that if the circuit does not function at all at any of these process extremes, the design is considered to have inadequate design margin (i.e., acceptable ranges of circuit parameters that result in fully functional IC's that meet all design specifications at specified PVT extremes) and must be redesigned. Indeed, in order to make sure that an IC design can be successfully fabricated in a selected implementation technology, a manufacturer may choose a very conservative design margin that results in a higher die yields of IC's but with less than optimum performance levels or power consumption.
In order to verify the robustness of an integrated circuit design, semiconductor manufacturers fabricate “corner lots”, which are groups of wafers that have had process parameters adjusted to various extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process called characterization. The results of these tests are analyzed in various known ways to determine the boundary limits beyond which a device begins to functionally fail or fails to meet the design specification for one or more particular combinations of environmental conditions.
One naming convention for process corners for field-effect transistor (FET) based IC's is to use two-letter designators, where the first letter refers to the N-channel MOSFET (NMOS) corner and the second letter refers to the P-channel (PMOS) corner. In this naming convention, three types of corners exist: “typical”, “fast”, and “slow”. Fast and slow corners exhibit carrier mobilities that are higher and lower than normal, respectively. There are therefore five possible corners: typical-typical (TT) (not really a corner of an N versus P mobility graph, but called a corner, anyway; the “TT” corner is the center “corner” where wafers are normally produced using typical process parameters), fast-fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). For example, a corner designated as “FS” denotes fast NMOS FETs and slow PMOS FETs.
The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at slower or faster clock frequencies, and are often grouped or “binned” as such. The last two corners (FS, SF) are called “skewed” corners, and are cause for concern. This is because one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge. Latching devices may then record incorrect values in a logic chain. In conventional IC design, design margins must be set so that an IC functions properly even within the skewed corners.
In addition to the transistors themselves, there are other on-chip variation (OCV) effects that manifest themselves at smaller technology nodes. These include PVT variation effects on on-chip interconnects as well as via structures. In addition, there are wafer-to-wafer and intra-wafer variations within the bulk material of wafers, both in initial form and post-doping.
Another problem in the translation of IC design to IC die is that in modern advanced transistor technologies, the power supply voltage is much lower compared to older technologies. For example, in 180 nm fabrication technology the recommended power supply voltage is 1.8V, while for 130 nm fabrication technology the recommended voltage is 1.2V, and for 28 nm fabrication technology the recommended voltage is 0.9V. In order to allow the implementation of fast transistors in these advanced technologies while the overdrive voltage is getting smaller and smaller due to reduced power supply voltages, the threshold voltage of the transistors is getting smaller and smaller in order to at least maintain or even increase the speed of the transistors. While decreasing the threshold voltage of the transistors in advanced technologies is mandatory and has a major speed impact on the technology behavior, it is also negatively impacts the current leakage performance of the technology: a smaller threshold voltage results in faster the devices, but faster devices have higher current leakage.
A number of approaches have been taken to compensate for the problems engendered by PVT dependent characteristics of advanced IC's. For example, one approach to dealing with performance differences caused by unique die-to-die response to an applied power supply voltage (i.e., where the same power supply voltage is provided to nominally identical but differently performing IC dies) is to provide for dynamic voltage scaling on an IC. FIG. 1 is a block diagram of a dynamic voltage scaling circuit 100 in accordance with the prior art. Dynamic voltage scaling (DVS) essentially includes the following:
Measurement of Local Voltage Dependent Die Characteristics: Each IC is provided with means to measure the speed of the implementation technology as a function of applied voltage. Such a means may be a voltage dependent test circuit 102, such as a ring oscillator based on standard cell digital gates (even for an analog IC). As is known in the art, the frequency (i.e., speed) of such ring oscillators is dependent on the applied voltage and the implementation characteristics of the individual devices comprising the ring oscillator structure. The ring oscillators should be based on the standard cells sizes used in the design (e.g., 7-track, 10-track, 12-track, 14-track, etc.). Each ring oscillator also should be implemented using transistor types similar to the ones used on the IC in the region of the ring oscillator, such as ultra-high Vt (UHVT), high Vt (HVT), standard Vt (SVT), low Vt (LVT), and ultra-low Vt (ULVT) transistors.
Comparison of the Measured Characteristics to a Standard: The output of the speed measuring means is compared to a reference value. For example, the output of the ring oscillators comprising the voltage dependent test circuit 102 may be compared against the output of a reference frequency source 104 (e.g., a crystal oscillator), using, for example, a comparator 106 comprising a delay-locked loop (DLL) to compare the reference frequency and the measured frequencies. The DLL output is a signal (generally a digital signal) that reflects the difference in frequency between the voltage dependent test circuit 102 and the reference frequency source 104.
Feedback Control of the Power Supply Voltage: The output of the comparison of the reference frequency and the measured frequency from the comparator 106 is applied to a means for controlling an external power supply to the IC, such as a variable voltage regulator 108, adjusting the applied power supply higher or lower depending on the result of the frequency comparison. For example, the output of the comparison may be a pulse width modulation (PWM) signal. The PWM duty cycle can be used in known fashion to increase or decrease the power supply voltage in order to match the speed of the ring oscillators to the reference frequency. If the ring oscillators are operating too slow, the applied power supply voltage is increased; conversely, if the ring oscillators are operating too fast, the applied power supply voltage is decreased. A typical adjustment range for a power supply using this approach is about ±10% (e.g., for a normalized voltage value of 1.0, the range is from about 0.9 to 1.1).
An IC design normally would have multiple DVS cells 110 distributed judicially across the IC die such that the voltage dependent test circuits 102 (e.g., ring oscillators) rather thoroughly reflect the transistor speed variations that occur across the dimensions of the die. When using multiple DVS cells 110, some economies of scale will be readily apparent to those skilled in the art, such as having only one reference frequency source 104 coupled to all DVS cells 110, and time sharing (multiplexing) a single comparator 104 with all DVS cells 110.
Despite such attempts to mitigate the effects of PVT dependent characteristics on the fabrication of advanced IC's, IC designers and manufacturers have still been conservative in their approach to setting margins for IC designs. While a conservative approach seemingly improves die yields, the result generally is larger dies, more power usage (and thus more heat), and slower circuits on average.
Accordingly, there is a need for an IC design approach that mitigates the effects of PVT dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits in comparison to the prior art. The present disclosure addresses this need.